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Welcome!
EE178 is a class for students interested in designing synchronous digital circuits using Xilinx FPGA devices. EE178 is a hands-on lab class where students will complete a number of exercises and projects in Verilog-HDL using the state-of-the-art Xilinx Vivado Design Suite software and a state-of-the art Xilinx Artix 7 FPGA device on the Digilent Basys3 board.

Students are responsible for providing their own equipment. You will need a Microsoft Windows 10 (64-bit) desktop or laptop, and should anticipate spending $80 on lab equipment in lieu of a required textbook.

It is my personal goal to make EE178 the best undergrad elective in the Electrical Engineering department. To this end, I appreciate any constructive feedback you might like to give. Please don't hesitate to contact me.

If you are from another class, another university, or even another universe, I encourage you to use the material here if it helps you learn something about the use of Xilinx FPGAs.
Handouts
1 Class Syllabus
2 Lecture Module 1
3 Lecture Module 2
4 Lecture Module 3
5 Lecture Module 4
6 Lecture Module 5
7 Lab #1
8 Lab #2
9 Lab #3
10 Lab #4
11 Lab #4 Files
12 Lab #5
13 Lab #6
14 Lab #6 Files
15 Lab #7
16 Lab #7 Files
17 Lab #8
18 Lab #8 Files
Forum
Discussion Group
This site last updated: 08/24/2016.